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1 ltc1412 12-bit, 3msps, sampling a/d converter the ltc ? 1412 is a 12-bit, 3msps, sampling a/d con- verter. this high performance device includes a high dynamic range sample-and-hold and a precision refer- ence. operating from 5v supplies it draws only 150mw. the 2.5v input range is optimized for low noise and low distortion. most high performance op amps also perform best over this range, allowing direct coupling to the analog inputs and eliminating the need for special translation circuitry. outstanding ac performance includes 72db s/(n + d) and 82db sfdr at the nyquist input frequency of 1.5mhz. the unique differential input sample-and-hold can acquire single-ended or differential input signals up to its 40mhz bandwidth. the 60db common mode rejection allows users to eliminate ground loops and common mode noise by measuring signals differentially from the source. the adc has a high speed 12-bit parallel output port. there is no pipeline delay in the conversion results. a separate convert start input and converter status signal (busy) ease connections to fifos, dsps and microprocessors. a digital output driver power supply pin allows direct con- nection to 3v logic. descriptio n u features typical applicatio n u 12-bit adc 12 5v optional 3v logic supply 10 m f av dd dv dd ov dd ognd 1412 ta01 dgnd d11 (msb) d0 (lsb) busy s/h buffer ltc1412 4.0625v 2k ?v 2.5v reference timing and logic output buffers ? ? cs convst agnd v ss 10 m f 10 m f v ref comp a in a in + effective bits and signal-to-noise + distortion vs input frequency input frequency (hz) 2 effective number of bits 4 6 8 10 1k 100k 1m 10m 1412 g01 0 10k 12 s/(n + d) (db) 62 74 56 68 n telecommunications n digital signal processing n mulitplexed data acquisition systems n high speed data acquisition n spectrum analysis n imaging systems applicatio n s u , ltc and lt are registered trademarks of linear technology corporation. n sample rate: 3msps n 72db s/(n + d) and 82db sfdr at nyquist n 0.35lsb inl and 0.25lsb dnl (typ) n power dissipation: 150mw n external or internal reference operation n true differential inputs reject common mode noise n 40mhz full power bandwidth sampling n 2.5v bipolar input range n no pipeline delay n 28-pin ssop package
2 ltc1412 absolute m axi m u m ratings w ww u package/order i n for m atio n w u u av dd = dv dd = v dd (notes 1, 2) supply voltage (v dd ) ................................................. 6v negative supply voltage (v ss )................................. C 6v total supply voltage (v dd to v ss ) .......................... 12v analog input voltage (note 3) ......................... (v ss C 0.3v) to (v dd + 0.3v) digital input voltage (note 4) .......... (v ss C 0.3v) to 10v digital output voltage ........ (v ss C 0.3v) to (v dd + 0.3v) power dissipation .............................................. 500mw operating temperature range ltc1412c................................................ 0 c to 70 c ltc1412i ............................................ C 40 c to 85 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c order part number t jmax = 110 c, q ja = 95 c/ w 1 2 3 4 5 6 7 8 9 10 11 12 13 14 top view g package 28-lead plastic ssop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 a in + a in v ref refcomp agnd d11 (msb) d10 d9 d8 d7 d6 d5 d4 dgnd av dd dv dd v ss busy cs convst dgnd dv dd ov dd ognd d0 d1 d2 d3 consult factory for military grade parts. ltc1412cg ltc1412ig symbol parameter conditions min typ max units v in analog input range (note 9) 4.75v v dd 5.25v, C 5.25v v ss C 4.75v l 2.5 v i in analog input leakage current cs = high l 1 m a c in analog input capacitance between conversions 10 pf during conversions 4 pf t acq sample-and-hold acquisition time l 20 50 ns t ap sample-and-hold aperture delay time C 0.5 ns t jitter sample-and-hold aperture delay time jitter 1 ps rms cmrr analog input common mode rejection ratio C 2.5v < (a in C = a in ) < 2.5v 63 db with internal reference (notes 5, 6) cc hara terist ics co u verter parameter conditions min typ max units resolution (no missing codes) l 12 bits integral linearity error (note 7) l 0.35 1 lsb differential linearity error l 0.25 1 lsb offset error (note 8) 2 6 lsb l 8 lsb full-scale error 15 lsb full-scale tempco i out(ref) = 0 l 15 ppm/ c put u i a a u log (note 5)
3 ltc1412 (note 5) symbol parameter conditions min typ max units s/(n + d) signal-to-noise plus distortion ratio 100khz input signal 72.5 db 1.465mhz input signal 70 72 db thd total harmonic distortion 100khz input signal, first 5 harmonics C 90 db 1.465mhz input signal, first 5 harmonics C 80 db sfdr spurious free dynamic range 1.465mhz input signal 82 db imd intermodulation distortion f in1 = 29.37khz, f in2 = 32.446khz C 84 db full power bandwidth 40 mhz full linear bandwidth s/(n + d) 3 68db 4 mhz accuracy ic dy u w a symbol parameter conditions min typ max units v dd positive supply voltage (note 10) 4.75 5.25 v v ss negative supply voltage (note 10) C 4.75 C 5.25 v i dd positive supply current cs high l 12 16 ma i ss negative supply current cs high l 18 28 ma p d power dissipation l 150 220 mw (note 5) i ter al refere ce characteristics u uu parameter conditions min typ max units v ref output voltage i out = 0 2.480 2.500 2.520 v v ref output tempco i out = 0 15 ppm/ c v ref line regulation 4.75v v dd 5.25v 0.01 lsb/ v C 5.25v v ss C 4.75v 0.01 lsb/ v v ref output resistance 0.1ma ? i out ? 0.1ma 2 k w comp output voltage i out = 0 4.06 v power require e ts w u (note 5) symbol parameter conditions min typ max units v ih high level input voltage v dd = 5.25v l 2.4 v v il low level input voltage v dd = 4.75v l 0.8 v i in digital input current v in = 0v to v dd l 10 m a c in digital input capacitance 1.4 pf v oh high level output voltage v dd = 4.75v, i o = C 10 m a 4.75 v v dd = 4.75v, i o = C 200 m a l 4.0 4.71 v v ol low level output voltage v dd = 4.75v, i o = 160 m a 0.05 v v dd = 4.75v, i o = 1.6ma l 0.10 0.4 v i oz hi-z output leakage d11 to d0 v out = 0v to v dd , cs high l 10 m a c oz hi-z output capacitance d11 to d0 cs high (note 9) 7 pf i source output source current v out = 0v C 10 ma (note 5) digital i puts a n d outputs u u
4 ltc1412 ti i g characteristics w u (note 5) symbol parameter conditions min typ max units f sample(max) maximum sampling frequency l 3 mhz t throughput throughput time (acquisition + conversion) l 333 ns t conv conversion time l 240 283 ns t acq acquisition time l 20 50 ns t 1 cs to convst setup time (notes 9, 10) l 5ns t 2 convst low time (note 10) l 20 ns t 3 convst to busy delay c l = 25pf 5 ns l 20 ns t 4 data ready before busy - C20 0 20 ns l C25 25 ns t 5 delay between conversions (note 10) l 50 ns t 6 data access time after cs c l = 25pf 10 35 ns l 45 ns t 7 bus relinquish time 830 ns ltc1412c l 35 ns ltc1412i l 40 ns t 8 convst high time l 20 ns t 9 aperture delay of sample-and-hold C 1 ns the l denotes specifications which apply over the full operating temperature range; all other limits and typicals t a = 25 c. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all voltage values are with respect to ground with dgnd and agnd wired together (unless otherwise noted). note 3: when these pin voltages are taken below v ss or above v dd , they will be clamped by internal diodes. this product can handle input currents greater than 100ma below v ss or above v dd without latchup. note 4: when these pin voltages are taken below v ss they will be clamped by internal diodes. this product can handle input currents greater than 100ma below v ss without latchup. these pins are not clamped to v dd . note 5: v dd = 5v, f sample = 3mhz and t r = t f = 5ns unless otherwise specified. note 6: linearity, offset and full-scale specifications apply for a single- ended a in input with a in C grounded. note 7: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 8: bipolar offset is the offset voltage measured from C 0.5lsb when the output code flickers between 0000 0000 0000 and 1111 1111 1111. note 9: guaranteed by design, not subject to test. note 10: recommended operating conditions. ti i g diagra u w w data (n ?1) db11 to db0 convst busy cs 1412 td t 2 t conv t 3 t 1 t 5 t 4 t 6 t 7 data n db11 to db0 data (n + 1) db11 to db0 data
5 ltc1412 typical perfor a ce characteristics uw input frequency (hz) 10 120 distortion (db) ?0 ?0 0 100 1k 10k 1412 g03 ?0 ?0 100 3rd thd 2nd distortion vs input frequency spurious-free dynamic range vs input frequency input frequency (hz) 2 effective number of bits 4 6 8 10 1k 100k 1m 10m 1412 g01 0 10k 12 s/(n + d) (db) 62 74 56 68 s/(n + d) and effective number of bits vs input frequency frequency (hz) 10k ?0 spurious-free dynamic range (db) ?0 ?0 ?0 ?0 100k 1m 10m 1412 g04 ?0 ?0 ?0 100 ?0 0 signal-to-noise ratio vs input frequency input frequency (hz) 10k 40 signal-to-noise ratio (db) 60 80 100k 1m 10m 1412 g02 20 30 50 70 10 0 integral nonlinearity vs output code output code 0 1.0 inl (lsbs) 0.5 0 0.5 1.0 512 1024 1536 2048 1412 g07 2560 3072 3584 4096 intermodulation distortion plot frequency (khz) 0 200 400 600 800 1000 1200 1400 110 amplitude (db) 100 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 1412 g05 ?0 ?0 f smpl = 3mhz f in1 = 85.693359khz f in2 = 114.990234khz differential nonlinearity vs output code output code 0 1.0 dnl (lsbs) 0.5 0 0.5 1.0 512 1024 1536 2048 1412 g06 2560 3072 3584 4096 frequency (khz) 0 200 400 600 800 1000 1200 1400 120 amplitude (db) 100 ?0 ?0 ?0 0 1412 f02a ?0 f smpl = 3msps f in = 97.412khz sfdr = 93.3db sinad = 73db nonaveraged, 4096 point fft, input frequency = 100khz frequency (khz) 0 200 400 600 800 1000 1200 1400 120 amplitude (db) 100 ?0 ?0 ?0 0 1412 f02b ?0 f smpl = 3msps f in = 1.419khz sfdr = 83db sinad = 72.5db snr = 73db nonaveraged, 4096 point fft, input frequency = 1.45khz
6 ltc1412 typical perfor a ce characteristics uw ripple frequency (hz) ?0 amplitude of power supply feedthrough (db) ?0 0 ?00 ?0 ?0 10k 100k 1m 10m 1412 g08 ?20 1k v ss v dd dgnd power supply feedthrough vs ripple frequency input frequency (hz) 20 common mode rejection (db) 40 50 70 80 1k 100k 1m 10m 1412 g09 0 10k 60 30 10 input common mode rejection vs input frequency pi n fu n ctio n s uuu a in + (pin 1): positive analog input. 2.5v input range when a in C is grounded. 2.5v differential if a in C is driven. a in C (pin 2): negative analog input. can be grounded or driven differentially with a in + . v ref (pin 3): 2.5v reference output. refcomp (pin 4): 4.06v reference bypass pin. bypass to agnd with 10 m f ceramic (or 10 m f tantalum in parallel with 0.1 m f ceramic). agnd (pin 5): analog ground. d11 to d4 (pins 6 to 13): three-state data outputs. dgnd (pin 14): digital ground for internal logic. d3 to d0 (pins 15 to 18): three-state data outputs. ognd (pin 19): digital ground for the output drivers. ov dd (pin 20): positive supply for the output drivers. tie to pin 28 when driving 5v logic. tie to 3v when driving 3v logic. dv dd (pin 21): 5v positive supply. tie to pin 28. bypass to agnd with 0.1 m f ceramic. dgnd (pin 22): digital ground for internal logic. convst (pin 23): conversion start signal. this active low signal starts a conversion on its falling edge. cs (pin 24): chip select. this input must be low for the adc to recognize the convst inputs. busy (pin 25): the busy output shows the converter status. it is low when a conversion is in progress. v ss (pin 26): C 5v negative supply. bypass to agnd with 10 m f ceramic (or 10 m f tantalum in parallel with 0.1 m f ceramic). dv dd (pin 27): 5v positive supply. tie to pin 28. av dd (pin 28): 5v positive supply. bypass to agnd with 10 m f ceramic (or 10 m f tantalum in parallel with 0.1 m f ceramic).
7 ltc1412 fu n ctio n al block diagra uu w 12-bit capacitive dac comp ref amp 2.5v ref 2k refcomp (4.06v) c sample c sample ? ? d11 d0 busy control logic internal clock convst cs zeroing switches ov dd ognd av dd dv dd a in + a in v ref agnd dgnd 12 1412 bd + successive approximation register output latches test circuits 1k c l c l dbn a) hi-z to v oh and v ol to v oh dbn 1k 5v b) hi-z to v ol and v oh to v ol 1412 tc01 1k 100pf dbn a) v oh to hi-z 100pf dbn 1k 5v b) v ol to hi-z 1412 tc02 load circuits for access timing load circuits for output float delay applicatio n s i n for m atio n wu u u conversion details the ltc1412 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 12-bit parallel output. the adc is complete with a precision reference and an internal clock. the control logic provides easy interface to microproces- sors and dsps. (please refer to the digital interface section for the data format.) conversion start is controlled by the cs and convst inputs. at the start of the conversion the successive approximation register (sar) is reset. once a conversion cycle has begun it cannot be restarted. during the conversion, the internal differential 12-bit capacitive dac output is sequenced by the sar from the most significant bit (msb) to the least significant bit (lsb). referring to figure 1, the a in + and a in C inputs are connected to the sample-and-hold capacitors (c sample ) during the acquire phase and the comparator offset is nulled by the zeroing switches. in this acquire phase, a minimum delay of 50ns will provide enough time for the
8 ltc1412 applicatio n s i n for m atio n wu u u comp c sample + c dac ? ? d11 d0 zeroing switches hold hold a in + a in c dac + c sample 12 1412 f01 + output latches v dac + v dac hold sample sample hold sar figure 1. simplified block diagram frequency (khz) 0 200 400 600 800 1000 1200 1400 120 amplitude (db) 100 ?0 ?0 ?0 0 1412 f02a ?0 f smpl = 3msps f in = 97.412khz sfdr = 93.3db sinad = 73db figure 2a. ltc1412 nonaveraged, 4096 point fft, input frequency = 100khz frequency (khz) 0 200 400 600 800 1000 1200 1400 120 amplitude (db) 100 ?0 ?0 ?0 0 1412 f02b ?0 f smpl = 3msps f in = 1.419khz sfdr = 83db sinad = 72.5db snr = 73db figure 2b. ltc1412 nonaveraged, 4096 point fft, input frequency = 1.45mhz to frequencies from above dc and below half the sampling frequency. figure 2 shows a typical spectral content with a 3mhz sampling rate and a 100khz input. the dynamic performance is excellent for input frequencies up to and beyond the nyquist limit of 1.5mhz. effective number of bits the effective number of bits (enobs) is a measurement of the resolution of an adc and is directly related to the s/(n + d) by the equation: n = [s/(n + d) C 1.76]/6.02 where n is the effective number of bits of resolution and s/(n + d) is expressed in db. at the maximum sampling rate of 3mhz the ltc1412 maintains near ideal enobs up to the nyquist input frequency of 1.5mhz. refer to figure 3. sample-and-hold capacitors to acquire the analog signal. during the convert phase the comparator zeroing switches open, putting the comparator into compare mode. the input switches connect the c sample capacitors to ground, transferring the differential analog input charge onto the summing junction. this input charge is successively com- pared with the binary-weighted charges supplied by the differential capacitive dac. bit decisions are made by the high speed comparator. at the end of a conversion, the differential dac output balances the a in + and a in C input charges. the sar contents (a 12-bit data word) which represents the difference of a in + and a in C are loaded into the 12-bit output latches. dynamic performance the ltc1412 has excellent high speed sampling capabil- ity. fft (fast four transform) test techniques are used to test the adcs frequency response, distortion and noise at the rated throughput. by applying a low distortion sine wave and analyzing the digital output using an fft algo- rithm, the adcs spectral content can be examined for frequencies outside the fundamental. figure 2 shows a typical ltc1412 fft plot. signal-to-noise ratio the signal-to-noise plus distortion ratio [s/(n + d)] is the ratio between the rms amplitude of the fundamental input frequency to the rms amplitude of all other frequency components at the a/d output. the output is band limited
9 ltc1412 applicatio n s i n for m atio n wu u u produce intermodulation distortion (imd) in addition to thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. if two pure sine waves of frequencies fa and fb are applied to the adc input, nonlinearities in the adc transfer func- tion can create distortion products at the sum and differ- ence frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. for example, the 2nd order imd terms include (fa + fb). if the two input sine waves are equal in magni- tude, the value (in decibels) of the 2nd order imd products can be expressed by the following formula: imd f f f amplitude at ab b + () = () 20 log amplitude at f f a a input frequency (hz) 2 effective number of bits 4 6 8 10 1k 100k 1m 10m 1412 g01 0 10k 12 s/(n + d) (db) 62 74 56 68 peak harmonic or spurious noise the peak harmonic or spurious noise is the largest spec- tral component excluding the input signal and dc. this value is expressed in decibels relative to the rms value of a full-scale input signal. full power and full linear bandwidth the full power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3db for a full-scale input signal. the full linear bandwidth is the input frequency at which the s/(n + d) has dropped to 68db (11 effective bits). the ltc1412 has been designed to optimize input bandwidth, allowing the adc to undersample input signals with fre- figure 3. effective bits and signal/(noise + distortion) vs input frequency total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency. thd is expressed as: thd vv = +++ 20 3 2 4 2 log v . . .v v 2 2 n 2 1 where v1 is the rms amplitude of the fundamental fre- quency and v2 through vn are the amplitudes of the second through nth harmonics. thd vs input frequency is shown in figure 4. the ltc1412 has good distortion performance up to the nyquist frequency and beyond. input frequency (hz) 10 120 distortion (db) ?0 ?0 0 100 1k 10k 1412 g03 ?0 ?0 100 3rd thd 2nd figure 4. distortion vs input frequency intermodulation distortion if the adc input signal consists of more than one spectral component, the adc transfer function nonlinearity can frequency (khz) 0 200 400 600 800 1000 1200 1400 110 amplitude (db) 100 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 1412 g05 ?0 ?0 f smpl = 3mhz f in1 = 85.693359khz f in2 = 114.990234khz figure 5. intermodulation distortion plot
10 ltc1412 applicatio n s i n for m atio n wu u u quencies above the converters nyquist frequency. the noise floor stays very low at high frequencies; s/(n + d) becomes dominated by distortion at frequencies far beyond nyquist. driving the analog input the differential analog inputs of the ltc1412 are easy to drive. the inputs may be driven differentially or as a single- ended input (i.e., the a in C input is grounded). the a in + and a in C inputs are sampled at the same instant. any unwanted signal that is common mode to both inputs will be reduced by the common mode rejection of the sample-and-hold circuit. the inputs draw only one small current spike while charging the sample-and-hold capacitors at the end of conversion. during conversion, the analog inputs draw only a small leakage current. if the source impedance of the driving circuit is low then the ltc1412 inputs can be driven directly. as source impedance increases so will acquisition time (see figure 6). for minimum acquisition time, with high source impedance, a buffer amplifier must be used. the only requirement is that the amplifier driving the analog input(s) must settle after the small current spike before the next conversion starts (settling time must be 50ns for full throughput rate). frequency. for example, if an amplifier is used in a gain of 1 and has a unity-gain bandwidth of 50mhz, then the output impedance at 50mhz should be less than 100 w . the second requirement is that the closed-loop bandwidth must be greater than 40mhz to ensure adequate small- signal settling for full throughput rate. if slower op amps are used, more settling time can be provided by increasing the time between conversions. the best choice for an op amp to drive the ltc1412 will depend on the application. generally applications fall into two categories: ac applications where dynamic specifica- tions are most critical and time domain applications where dc accuracy and settling time are most critical. the following list is a summary of the op amps that are suitable for driving the ltc1412. more detailed information is available in the linear technology databooks and on the linearview tm cd-rom. lt ? 1223: 100mhz video current feedback amplifier. 6ma supply current. 5v to 15v supplies. low noise. good for ac applications. lt1227: 140mhz video current feedback amplifier. 10ma supply current. 5v to 15v supplies. low noise. best for ac applications. lt1229/lt1230: dual and quad 100mhz current feed- back amplifiers. 2v to 15v supplies. low noise. good ac specifications, 6ma supply current each amplifier. lt1360: 50mhz voltage feedback amplifier. 3.8ma sup- ply current. 5v to 15v supplies. good ac and dc specifications. 70ns settling to 0.5lsb. lt1363: 70mhz, 1000v/ m s op amps. 6.3ma supply cur- rent. good ac and dc specifications. 60ns settling to 0.5lsb. lt1364/lt1365: dual and quad 70mhz, 1000v/ m s op amps. 6.3ma supply current per amplifier. 60ns settling to 0.5lsb. input filtering the noise and the distortion of the input amplifier and other circuitry must be considered since they will add to the ltc1412 noise and distortion. the small-signal band- source resistance ( w ) 10 0.01 acquisition time ( m s) 0.1 1 10 100 1k 1412 f06 10k 100k figure 6. acquisition time vs source resistance choosing an input amplifier choosing an input amplifier is easy if a few requirements are taken into consideration. first, to limit the magnitude of the voltage spike seen by the amplifier from charging the sampling capacitor, choose an amplifier that has a low output impedance (<100 w ) at the closed-loop bandwidth linearview is a trademark of linear technology corporation.
11 ltc1412 applicatio n s i n for m atio n wu u u width of the sample-and-hold circuit is 40mhz. any noise or distortion products that are present at the analog inputs will be summed over this entire bandwidth. noisy input circuitry should be filtered prior to the analog inputs to minimize noise. a simple 1-pole rc filter is sufficient for many applications. for example, figure 7 shows a 500pf capacitor from a in + to ground and a 100 w source resistor to limit the input bandwidth to 3.2mhz. the 500pf capacitor also acts as a charge reservoir for the input sample-and-hold and iso- lates the adc input from sampling glitch-sensitive circuitry. high quality capacitors and resistors should be used since these components can add distortion. npo and silver mica type dielectric capacitors have excellent linear- ity. carbon surface mount resistors can also generate distortion from self heating and from damage that may occur during soldering. metal film surface mount resis- tors are much less susceptible to both problems. when high amplitude unwanted signals are close in frequency to the desired signal frequency, a multiple pole filter is required. figure 7b shows a simple implementa- tion using an ltc1560-1 fifth-order elliptic continuous time filter. input range the 2.5v input range of the ltc1412 is optimized for low noise and low distortion. most op amps also perform best over this same range, allowing direct coupling to the ana- log inputs and eliminating the need for special translation circuitry. some applications may require other input ranges. the ltc1412 differential inputs and reference circuitry can ac- commodate other input ranges often with little or no addi- tional circuitry. the following sections describe the reference and input circuitry and how they affect the input range. internal reference the ltc1412 has an on-chip, temperature compensated, curvature corrected, bandgap reference that is factory trimmed to 2.500v. it is connected internally to a reference amplifier and is available at v ref (pin 3), see figure 8a. a 2k resistor is in series with the output so that it can be easily overdriven by an external reference or other cir- cuitry, see figure 8b. the reference amplifier gains the voltage at the v ref pin by 1.625 to create the required internal reference voltage. this provides buffering be- tween the v ref pin and the high speed capacitive dac. the reference amplifier compensation pin, refcomp (pin 4) must be bypassed with a capacitor to ground. the refer- ence amplifier is stable with capacitors of 1 m f or greater. for the best noise performance, a 10 m f ceramic or 10 m f tantalum in parallel with a 0.1 m f ceramic is recommended. figure 7b. 1mhz fifth-order elliptic lowpass filter ltc1412 a in + a in v ref refcomp agnd ltc1560-1 1412 f07b 1 2 3 4 1 2 3 4 8 7 6 5 5 10 m f v in ?v 5v 0.1 m f 0.1 m f figure 7a. rc input filter ltc1412 a in + a in v ref refcomp agnd 1412 f07a 1 2 3 4 5 10 m f 500pf 100 analog input figure 8a. ltc1412 reference circuit r2 40k r3 64k reference amp 10 f refcomp agnd v ref r1 2k 3 4 5 2.500v 4.0625v ltc1412 1412 f08a bandgap reference
12 ltc1412 applicatio n s i n for m atio n wu u u ltc1412 a in + analog input 5v a in v ref refcomp agnd 1412 f08b 1 2 3 4 5 10 m f v in v out lt1019a-2.5 ripple frequency (hz) ?0 amplitude of power supply feedthrough (db) ?0 0 ?00 ?0 ?0 10k 100k 1m 10m 1412 g08 ?20 1k v ss v dd dgnd mode voltage. thd will degrade as the inputs approach either power supply rail, from C 86db with a common mode of 0v to C75db with a common mode of 2.5v or C 2.5v. full-scale and offset adjustment figure 11a shows the ideal input/output characteristics for the ltc1412. the code transitions occur midway between successive integer lsb values (i.e., C fs/2 + 0.5lsb, C fs/2 + 1.5lsb, C fs/2 + 2.5lsb,...fs/2 C 1.5lsb, fs/2 C 0.5lsb). the output is twos complement binary with 1lsb = fs C (C fs)/4096 = 5v/4096 = 1.22mv. differential inputs the ltc1412 has a unique differential sample-and-hold circuit that allows rail-to-rail inputs. the adc will always convert the difference of a in + C (a in C ) independent of the common mode voltage. the common mode rejection holds up to extremely high frequencies, see figure 10. the only requirement is that both inputs cannot exceed the av dd or av ss power supply voltages. integral nonlinearity errors (inl) and differential nonlinearity errors (dnl) are independent of the common mode voltage, however, the bipolar zero error (bze) will vary. the change in bze is typically less than 0.1% of the common mode voltage. dynamic performance is also affected by the common in applications where absolute accuracy is important, offset and full-scale errors can be adjusted to zero. offset error must be adjusted before full-scale error. figure 11b shows the extra components required for full-scale error adjustment. zero offset is achieved by adjusting the offset applied to the a in C input. for zero offset error apply figure 10. cmrr vs input frequency figure 8b. using the lt1019-2.5 as an external reference the v ref pin can be driven with a dac or other means shown in figure 9. this is useful in applications where the peak input signal amplitude may vary. the input span of the adc can then be adjusted to match the peak input signal, maximizing the signal-to-noise ratio. the filtering of the internal ltc1412 reference amplifier will limit the bandwidth and settling time of this circuit. a settling time of 5ms should be allowed for after a reference adjustment. ltc1412 a in + analog input 1.25v to 3v differential a in v ref refcomp agnd 1412 f09 1 2 3 4 5 10 m f ltc1450 1.25v to 3v figure 9. driving v ref with a dac input voltage (v) output code 1412 f11a 111...111 111...110 111...101 000...000 000...001 000...010 fs ?1lsb fs ?1lsb figure 11a. ltc1412 transfer characteristics
13 ltc1412 applicatio n s i n for m atio n wu u u plane to the power supply should be low impedance. digital circuitry grounds must be connected to the digital supply common. low impedance analog and digital power supply lines are essential to low noise operation of the adc. the traces connecting the pins and bypass capaci- tors must be kept short and should be made as wide as possible. the ltc1412 has differential inputs to minimize noise coupling. common mode noise on the a in + and a in C leads will be rejected by the input cmrr. the a in C input can be used as a ground sense for the a in + input; the ltc1412 will hold and convert the difference voltage between a in + and a in C . the leads to a in + (pin 1) and a in C (pin 2) should be kept as short as possible. in applications where this is not possible, the a in + and a in C traces should be run side by side to equalize coupling. supply bypassing high quality, low series resistance ceramic, 10 m f bypass capacitors should be used at the v dd and refcomp pins. surface mount ceramic capacitors such as murata grm235y5v106z016 provide excellent bypassing in a small board space. alternatively 10 m f tantalum capacitors in parallel with 0.1 m f ceramic capacitors can be used. bypass capacitors must be located as close to the pins as possible. the traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. example layout figures 13a, 13b, 13c and 13d show the schematic and layout of an evaluation board. the layout demonstrates the proper use of decoupling capacitors and ground plane with a two layer printed circuit board. figure 12. power supply grounding practice ltc1412 a in + analog input a in v ref refcomp agnd 1412 f11b 1 2 3 r4 100 w r2 50k r3 24k ?v r6 24k r1 50k r5 47k 4 5 10 m f figure 11b. offset and full-scale adjust circuit C 0.61mv (i.e., C 0.5lsb) at a in + and adjust the offset at the a in C input until the output code flickers between 0000 0000 0000 and 1111 1111 1111. for full-scale adjust- ment, an input voltage of 2.49817v (fs/2 C 1.5lsbs) is applied to a in + and r2 is adjusted until the output code flickers between 0111 1111 1110 and 0111 1111 1111. board layout and bypassing to obtain the best performance from the ltc1412, a printed circuit board with ground plane is required. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital line alongside an analog signal line. an analog ground plane separate from the logic system ground should be established under and around the adc. pin 5 (agnd), pins 22 and 14 (dgnd) and pin 19 (ognd) and all other analog grounds should be connected to this single analog ground point. the refcomp bypass capaci- tor and the dv dd bypass capacitor should also be con- nected to this analog ground plane, see figure 12. all analog circuitry grounds should be terminated to this analog ground plane. the ground return from the ground 1412 f12 a in + agnd refcomp v ss av dd ltc1412 digital system analog input circuitry 5 4 2 26 ov dd dv dd 20 21, 27 28 ognd dgnd 14, 22 19 power supply ground 1 0.1 m f a in 0.1 m f 0.1 m f 10 m f analog ground plane + + 10 m f 10 m f + +
14 ltc1412 applicatio n s i n for m atio n wu u u ov dd ov dd + e3 7v to 15v e2 gnd e4 optional a + a v cc v cc v ss jp7 u1 ltc1412 b[00:11] u6 74hc574 u7 74hc574 56 u5f 74hc14 u5c 74hc14 9 8 rdy u5d 74hc14 d11 d1 d3 d5 d7 d9 d11 d10 d8 d6 d4 d2 d0 d11 jp1 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d[0:11] r1, 1.2k r2, 1.2k r3, 1.2k r4, 1.2k r5, 1.2k r6, 1.2k r7, 1.2k r9, 1.2k r8, 1.2k r10, 1.2k r11, 1.2k r12, 1.2k 11 10 u5e 74hc14 r13 1k 12 13 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d10 d9 d8 d7 d6 d5 d4 d0 d1 d2 d3 d11 19 18 17 16 15 14 13 12 19 18 17 16 15 14 13 12 q0 q1 q2 q3 q4 q5 q6 q7 q0 q1 q2 q3 q4 q5 q6 q7 0e 0e notes: unless otherwise specified 1. all resistor values 1/8w, 5% smt 2. all capacitor values 50v, 20% smt v ss v cc clk j3 v in u2 lt1121-5 u4 lt1175 d13 ss12 r17 10k r18 10k r19 51 w r16 51 w r15 51 w u5a 74hc14 jp8 u5b 74hc14 c6 470pf c10 1 f 16v c11 10 m f 16v c13 0.1 f c20 15pf c14 0.1 f c1 22 f 10v tab gnd 1 42 3 c2 0.1 m f c9 0.1 m f u3 lt1363 3 2 1 23 4 6 7 1 8 5 4 j1 j2 jp6 v out 1 2 3 4 5 14 23 24 25 20 19 26 27 28 6 7 8 9 10 11 12 13 15 16 17 18 22 21 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b0 b1 b2 b3 b11 b10 b9 b8 b7 b6 b5 b4 1 11 2 3 4 5 6 7 8 9 1 11 2 3 4 5 6 7 8 9 d11 (msb) d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 ognd ov dd +a in ? in v ref refcomp agnd dgnd convst cs busy dv dd dgnd v ss dv dd av dd jp5 v cc 3.3v 3.3v + ov dd c5 10 f 10v c4 0.1 f + 1412 f13a jp2 header 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 c8 0.1 f ov dd c7 0.1 f gnd gnd 12 + c3 0.1 f jp3 jp4 r14 20 w shdn input input lim2 sense out lim4 gnd 1 8 4 3 27 65 e1 7v to 15v d14 ss12 + c12 22 f 10v v ss ov dd c19 0.1 f u5 decoupling clk clk 20 10 20 10 21 21 12 12 2 1 figure 13a. ltc1412 demonstration board features analog input signal buffer, 3msps, parallel data output 12-bit adc, data latches and led binary data display. latched conversion data is available on the 16-pin header, p2
15 ltc1412 applicatio n s i n for m atio n wu u u figure 13b. component side silkscreen figure 13c. component side figure 13d. solder side information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
16 ltc1412 ? linear technology corporation 1998 1412f lt/tp 0798 4k ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com part number resolution speed comments 16-bit ltc1604 16 333ksps 2.5v input range, 5v supply ltc1605 16 100ksps 10v input range, single 5v supply 14-bit ltc1419 14 800ksps 150mw, 81.5db sinad and 95db sfdr ltc1416 14 400ksps 75mw, low power with excellent ac specs ltc1418 14 200ksps 15mw, single 5v, serial/parallel i/o 12-bit ltc1410 12 1.25msps 150mw, 71.5db sinad and 84db thd ltc1415 12 1.25msps 55mw, single 5v supply ltc1409 12 800ksps 80mw, 71.5db sinad and 84db thd ltc1279 12 600ksps 60mw, single 5v or 5v supply ltc1404 12 600ksps high speed serial i/o in so-8 package ltc1278-5 12 500ksps 75mw, single 5v or 5v supply ltc1278-4 12 400ksps 75mw, single 5v or 5v supply ltc1400 12 400ksps high speed serial i/o in so-8 package package descriptio n u dimensions in inches (millimeters) unless otherwise noted. g package 28-lead plastic ssop (0.209) (ltc dwg # 05-08-1640) related parts g28 ssop 0694 0.005 ?0.009 (0.13 ?0.22) 0 ?8 0.022 ?0.037 (0.55 ?0.95) 0.205 ?0.212** (5.20 ?5.38) 0.301 ?0.311 (7.65 ?7.90) 1234 5 6 7 8 9 10 11 12 14 13 0.397 ?0.407* (10.07 ?10.33) 25 26 22 21 20 19 18 17 16 15 23 24 27 28 0.068 ?0.078 (1.73 ?1.99) 0.002 ?0.008 (0.05 ?0.21) 0.0256 (0.65) bsc 0.010 ?0.015 (0.25 ?0.38) dimensions do not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimensions do not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * **

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